Clock signals may be used in electronic circuits for timing the operation of various internal circuits. For example, in synchronous memory devices, external clock signals may be provided to a memory device and internally distributed to various circuits so that internal operations in the memory device can be synchronized to the operation of external devices. Examples of such synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (“SDRAMs”), synchronous static random access memories (“SSRAMs”), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors.
A number of different approaches have been used to synchronize internal clock signals to external clock signals, including the use of delay-locked loops (“DLLs”). Although a single clock edge transition, such as the rising edge of clock signals, may be used to control the timing of internal operations, both the rising edges and the falling edges of clock signals may also be used for this purpose. However, as the frequency of clock signals increase, variations in the duty cycle of clock signals may introduce unacceptable timing errors. Clock signals may ideally have a duty cycle of 50% so that the timing of internal operations synchronized to both the rising and falling edges of the clocks signals are equally spaced in time from each other. However, in some applications a duty cycle of other than 50% may be desired. Variations in the duty cycle from a specific value may introduce timing errors because operations that are synchronized to the falling edges of the clock signals may occur too early or too late relative to the occurrence of operations that are synchronized to the rising edge of the clock signals. For example, if the rising edges of a clock signal are used to output odd bits of read data from a memory device and the falling edges of the clock signal are used to output intervening even bits of read data, variations in the duty cycle may vary the period of time that valid read data bits are output from the memory device. Yet the duration of the period that valid read data must be provided, a parameter known as the “output hold time” and abbreviated “tOH,” may have a specified minimum value. Variations in the duty cycle of a clock signal used in this manner may therefore cause the memory device to fail to meet required performance specifications.
Duty cycle correction circuits have been developed to correct duty cycle variations to a 50% or some other specific duty cycle. Prior art dynamic duty cycle or tOH correction circuits may correct the duty cycle by delaying a clock signal and adjusting the magnitude of the delay. This delay may be provided by coupling the clock signal through a large number of series-coupled logic gates or inverters, and the delay may be adjusted by varying the number of gates or inverters through which the clock signal is coupled. Unfortunately, coupling clock signals, particularly high frequency clock signals, through a large number of gates or inverters may consume substantial power because power may be consumed as each of many gates or inverters switches responsive to each transition of the clock signal. Therefore, prior art duty cycle correction circuits used in clock generators and other circuits may consume excessive power.